In a DRAM system, the DQ bits within a nibble or byte can be re-ordered to help board routing and system integration issues. The dual inline memory modules (DIMM) specification and DRAM specification groups have created a situation where it is difficult to provide system integration without adding cost to the system. As of now there are no re-ordering restrictions and there are no defined re-ordering methodologies. Additionally, the re-ordering within each byte can be unique, and the re-ordering for each rank can be different. With features like CRC (Cyclic Redundancy Check), the order of the data is significant. The CRC algorithm relies on a specific bit order and will not function correctly if the DRAM and system-on-a chip (SoC) do not create the CRC bits based on the same DQ order. There are several conventional solutions to this issue. They are described below:
1. Do not allow bits within a byte to be reordered. This will require all double data rate 4 (DDR4) DIMM and board manufacturers to never re-order DQ bits; any vendor who does not adhere to this rule will create an incompatibility issue. This will also limit the ability of these vendors to optimally route the DQ bus to minimize system integration issues, which will limit the maximum achievable frequency of a system and/or maximum loading of a system. The maximum loading will limit the maximum DRAM density that can be utilized.
2. Limit DQ re-ordering to a defined subset. This will also require all DDR4 DIMM and board vendors to adhere to this limitation; any vendor who does not will create an incompatibility issue. For a system provider, this scenario is not attractive. Additionally, predefining the re-ordering will limit what can be done to minimize SI issues.
3. Use a serial presence detect device (storage element) on the DIMM to store the bit reordering for all DRAM devices on the DIMM. Each 8-bits on each rank can be re-ordered. A DIMM is typically 64-bits wide and can have up to 4 ranks of memory. This scenario has 32 unique sets of 8 DQ bits that could be reordered. The reordering can be unique for each set. Consequently the amount of storage to hold the reordering information is large and may require a larger storage element (EEPROM, etc.). A larger storage device will add to the overall cost of a system.
Additionally, reordering can occur on non-DIMM systems based on the routing between the DDR4 device and the SoC. In this scenario, an SPD device does not exist and would be very costly to add to the system. A solution that can be implemented to the satisfaction of DRAM, DIMM, and System vendors alike has not been provided.
DDR DIMM (Dual-Inline Memory Modules) commonly reorder the bits within a byte lane for better signal integrity. While no specific proposals for DDR4 DIMMs have been made yet, it is expected that DDR4 DIMM manufacturers will want to be able to reorder the DRAM bits within each byte lane for better signal integrity. Further, the SoC package or the printed circuit board (PCB) designer may also wish to reorder DRAM bits within a byte lane for signal integrity purposes.
Consequently, the SoC must understand how the DQ bits are routed and potentially re-ordered from the SoC output to the DRAM inputs. Accordingly what is desired is a system and method for providing re-ordering of the bits provided to a memory system that addresses the above identified issues. The system and method should cost effective, easily implemented and adaptable to existing environments.
The present invention addresses such a need.